Can I save time using Enhancement Mode FET testing on In-Circuit Test Systems with the 7.10p software?

Can I save time using Enhancement Mode FET testing on In-Circuit Test Systems with the 7.10p software?

Medalist 3070 and i3070 users can save time due to the automatic test generation for enhancement mode FETs the software release 7.10p. Prior to this software release, the unpowered nfetr and pfetr tests for FETs were effective only for JFETs and depletion mode MOSFETs as the gate pin is grounded by a guard and a channel is already present. In an enhancement mode MOSFET, a positive gate-source voltage must be applied before a channel is formed. The new test automatically generated for enhancement mode MOSFETs is a powered analog test that consists of two subtests: one that tests the MOSFET when it is turned on and the other when it is turned off. Enhancement-mode MOSFETs can be specified under the FET section in the board file, by adding the E option and furnishing a gate voltage. They do not need to be specified as pin libraries. In the following board file example, the gate voltage is specified to be 2 V. The "EN 2" option on the following line describes this FET as an N-channel enhancement mode FET with a gate voltage of 2V. FET "QF201" 100 20 EN 2 PN"2N4393" "FET"; _______________________________________________________________________________ An example of a generic powered analog test for an N-type enhancement-mode MOSFET follows: !!!! 2 0 1 1166516992 0000 ! IPG: rev 07.10p Tue Jun 3 16:29:53 2008 ! ! "qf201" test: Powered Analog test for enhancement mode MOSFET ! high 100, low 20, gate 2, type N test powered analog warning "Generic enhancement mode MOSFET test: debug with caution." disconnect all clear connect s to nodes "QF201-D" ! Drain connect a to nodes "QF201-G" ! Gate connect i to nodes "QF201-D" ! Drain connect l to nodes "QF201-S" ! Source source dcv, am 2*1.1, terminated 500, ico 0, on test "On" test "Off" end test subtest "On" Exp_On = 0.0 auxiliary dcv, am 2*1.1, on detector dcv, expect Exp_On measure Exp_On+1.0, Exp_On-1.0 end subtest   For more information about ICT system, please visit Keysight In-circuit test (ICT) System

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